試作チップ

LDPC Decoder Chip for WiMAX

6.72Gb/s 8pJ/bit/iteration WPAN LDPC Decoder

耐タンパ付きAES暗号チップ

4kx2k@60fps H.264/AVC Video Decoder Chip

1080p@60fps Multi-Standard Video Decoder Chip

1409mw H.264 Video Encoder

189mw@820Mb/s OFDM/UWB Baseband LSI

1.14Gb/s 15360bit
LDPC復号器

ME Engine for MPEG2/4

Scalable VBSME Architecture

1-D Systolic Array VBSME Architecture

Integer ME Engine for 1080HD

192bit Elliptic Curve Cryptography

Low Power RSA Cryptographic Co-Processor

Memory Efficient LDPC Decoder

LDPC Decoder Accelerating Message-Passing Schedule

LDPC Decoder Chip for WiMAX　

	Technology Chip area Core area Density Frequency Supply Throughput Measured Power Enengy	SMIC 65nm Low Leakage LVT 2.1mmx2.6mm 1.6mmx2.1mm 83.1% 11MHz 110MHz 0.8V 1.2V 105.6Mbps 1056Mbps 8.3mW 115mW 7.8pJ/bit/iter 10.9pJ/bit/iter
	Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Dajiang Zhou, Satoshi Goto, “A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS”, IEEE A-SSCC 2011

6.72Gb/s 8pJ/bit/iteration WPAN LDPC Decoder　

	Technology Supply Die Size Gates Core Power	Fujitsu 65nm CMOS 1.2V Core, 3.3V I/O 2.1x2.1mm2 430K 537.6mW@400MHz
	Zhixiang CHEN, Xiao PENG, Xiongxin ZHAO, Qian XIE, Leona OKAMURA, Dajiang ZHOU and Satoshi GOTO on VLSI-DAT 2011 Best Paper Award, 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Bronze Award, 1st Chip Design Competition, 2011 International Symposium on Integrated Circuits

耐タンパ付きAES暗号チップ　

	Technology Core power	SMIC 90nm CMOS 0.61bps/Hz 2.05uW@100KHz
	Satoshi Goto, Yibo Fan, ISPLED 2010

4kx2k@60fps H.264/AVC Video Decoder Chip

	Technology Supply voltage Die size Gates SRAM Core power	SMIC 90nm CMOS 1.0V Core, 1.8V/2.5V I/O 4x4mm2 662K 59.6KB 189mW@175MHz (4096x2160@60fps)
	Dajiang Zhou, Jinjia Zhou, Xun He, Ji Kong, Jiayi Zhu, Peilin Liu, and Satoshi Goto, Symposium on VLSI Circuits 2010

1080p@60fps Multi-Standard Video Decoder Chip

	Technology Video Format Through Put Gate Count #DRAM Pins System Power	SMIC 180nm MPEG2, H.264, AVS 1920x1080@60fps/200MHz 367Kk 70 468mw
	D. Zhou, Z. You, J. Zhu, J. Kong, Y. Hong, X. Chen2, X. He, C. Xu2, H. Zhang, J. Zhou, N. Deng, P. Liu, and S. Goto, VLSI Symposium June 2009

1409mw H.264 Video Encoder

	Technology Gate Count SRAM Core Power Profile Search range Inter mode	130nm 1140k 108k 1219mw Baseline 192x128 8x8, 8x16, 16x8, 16x16
	Zhenyu Liu, Yang Song,Ming Shao, Shen Li, Lingfeng Li, Shunichi Ishiwata,Masaki Nakagawa, Satoshi Goto and Takeshi Ikenaga, IEEE . SC 2009/2

189mw@820Mb/s OFDM/UWB Baseband LSI

	Technology Die Size Gate Count On-chip Memory #Subcarrier Code length Clock Throughput Power	130nm 5.0mm x 5.0mm 1.58M 84.5k 1024 648 147MHz 820Mb/s 189mw/391mw
	Shinsuke Ushiki, Koichi Nakamura, Kazunori Shimizu, Qi Wang, Yuta Abe, Satoshi Goto and Takeshi Ikenaga（ASSCC 2008）

1.14Gb/s 15360bit LDPC符号復号器

	Technology Core Size Code lengh Throughput	ASPLA 90nm 5.0mm x 5.0mm 15360bit 1.14Gb/s
	清水一範、池永剛、後藤敏、"1.14Gb/s 15360bit LDPC符号復号器", 第９回LSI IPデザイン・アワード, Apr. 2007

Motion Estimation HW Engine for MPEG2/4

	Technology Core Size # of Pins Gate Count SRAM Clock Frequency Supply Voltage	TSMC 0.18um CMOS, 6M 1.99mm x 1.99mm 73(without P/G) 19.6k CB:2kbit RB:4kbit QCIF(15fps):>4.16MHz CIF(30fps):>33.3MHz 1.6V
	Shen Li, Satoshi Goto, Takeshi Ikenaga, Hideki Takeda, Masataka Matsui, "A Hardware Implementation of a Content-based motion estimation Algorithm for real-time MPEG-4 video coding," IEICE Trans. on Fundamentals Vol. E89-A, No.4, pp. 932-940, April, 2006.

Scalable VBSME Architecture

	Technology # of PEs Gate Count Frequency	TSMC 0.18um CMOS, 6M 16 / PE Group 21K 2-NAND gates 237.5 MHz
	Yang Song, Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga, "Scalable VLSI Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC," IEICE Trans. on Fundamentals, Vol. E89A, No.4, pp. 979-988, April 2006.

1-D Systolic Array VBSME Architecture

		Technology Processing Capability # of PEs Gate Count SRAM Frequency Power	TSMC 0.18um CMOS, 6M CIF(352 x 288)@36fps 32 x 32 Search Range 32 51.7K 2-NAND gates 9.7K 2-NAND gates 266MHz 131.7mW @ 266MHz
		Yang Song, Zhenyu Liu, Takeshi Ikenaga, Satoshi Goto, "A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization, " IEICE Trans. on Fundamentals, Vol.E90-A, No.12, December 2006. (to appear)

Integer Motion Estimation Engine for 1080HD

	[ASIC] Technology Area Power [SiS-DRAM] Technology Area Power [SiIP] Technology Area	TSMC 0.18um CMOS, 6M 14.1mm x 7.1mm 2,383mW@200MHz 0.11um triple-well TLM 6.97mm x 5.06 mm 190mW @25MHz 0.5um DLM 15.68mm 14.54mm

Kouichi Kumagai, Changi Yang, Hitoshi Izumino, Nobuyuki Narita, Keisuke Shinjo, Shin-ichi Iwashita, Yuji Nakaoka, Tomohiro Kawamura, Hideo Komabashiri, Tsukasa Minato, Atsushi Ambo, Takamasa Suzuki, Zhenyu Liu, Yang Song, Satoshi Goto, Takeshi Ikenaga, Yoshihiro Mabuchi and Kenji Yoshida, "System-in-Silicon Architecture and its Application to H.264/AVC Motion Estimation for 1080HDTV," IEEE ISSCC Digest of Technical Papers, pp. 430-431, Feb., 2006.

192bit Elliptic Curve Cryptography Chip

	Technology Core Size Gate Count Frequency	ROHM0.35um CMOS, 3M 4.9mm x 4.9mm 74k 50MHz
	Nobuyuki Kobayashi, Tohru Hisakado, Jumpei Uchida, Satoshi Goto, Takeshi Ikenaga, Yukiyasu Tsunoo, "An Elliptic Curve Cryptography LSI with a high efficient computational unit over GF(p)," IEICE SCIS 2005, Jan., 2005.

Low Power RSA Cryptographic Co-Processor

	Technology Core Size Gate Count Key Size	TSMC 0.18um CMOS, 6M 2.2 mm x 2.2 mm 50k 2,048 bits
	Toru Hisakado, Nobuyuki Kobayashi, Satoshi Goto, Takeshi Ikenaga, Kunihiko Higashi, Ichiro Kitao, Yukiyasu Tsunoo," 61.5mW 2048-bit RSA Cryptographic Co-processor LSI based on N bit-wised Modular Multiplier", IEEE VLSI-DAT, April, 2006.

Memory Efficient LDPC Decoder

	Technology Core Size Gate Count SRAM Frequency Throughput Power	TSMC 0.18um CMOS, 6M 6.0 mm x 6.0 mm 206Kgates (core) 85,248 bits 147MHz 530Mb/s (10 itr.) 3.6 W
	Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga and Satoshi Goto, "High-Throughput Decoder for Low-Density Parity-Check Code," Proc. IEEE ASP-DAC 2006, pp. 112-113, Jan., 2006.

LDPC Decoder Accelerating Message-Passing Schedule

	Technology Core Size Gate Count SRAM Frequency Throughput Power	TSMC 0.18um CMOS, 6M 5.0 mm x 5.0 mm 96Kgates (core) 7,113,932um^2 120MHz 122 Mb/s 529 mW
	Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga and Satoshi Goto, "ASIC Implementation of LDPC Decoder Accelerating Message Passing Schedule," ACM/IEEE DAC/ISSCC, July. 2006. 43rd DAC/ISSCC Student Design Contest 1st place (Conceptual Category)


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