ASPDAC 2004 Tutorial Information

Date: Tuesday, January 27, 2004 (9:00 - 17:00)
Place: Pacifico Yokohama, Room (TBA)

Japanese Page

Registration Fee

                                       Member    non-Member   Student
Advance (full-day, 2 x half-day)      24,000     30,000       15,000
Advance (half-day)                    15,000     18,000        9,000

On-Site  (full-day, 2 x half-day)      28,000     34,000       17,000
On-Site  (half-day)                    17,000     20,000       10,000

Tutorial 1 (Full-day, 9:00 - 17:00)

"Recent Advances and Future Challenges in Design Verification,"
D. Pradhan (Univ. of Bristol, UK), M. Abadir (Motrola, USA) and R. Drechsler (Univ. of Bremen, Germany)

ABSTRACT: This tutorial will cover the recent advances in design verification and the future direction. It is well known that the design verification is becomming the major part of the design phase, and the applicaion of the formal verification methods makes sense. It will be useful to understand the basis of the formal verification method with the several application samples. The tutorial includes the following wide areas: Design flow, RTL-verification, Simulation-based techniques, basic concepts of equivalence checking, combinational equivalence checking, ATPG-based techniques, compare point matching, mitering, don't cares, solver overview (structural verification, BDD-based solvers, SAT-based solvers), Decision Diagrams (BDDs, zBDDs, word-level DDs). Also to be covered are Concepts in SAT solvers (backtrack-search algorithm, effective techniques, including non-chronological backtracking & Boolean constraint propagation), new EDA-related techniques (covering immediate implications, partial-clauses, local decisions & partial clauses). Finally, the Tutorial will give an overview of various commercially available tools, & their applicability. Also to be discussed are future challenges, such as design for verifiability & potential new directions.

Intended Audience: Practicing engineers, users, & academics, interested in the basic principles & current state-of-the-art.

Tutorial Summary: Providing an overview of recent developments as well as basic principles of equivalence checking, SAT-Solvers and verification. Also to provide perspective of practical industrial experiences in the use and development of the tools.
Tutorial 2 (Full-day, 9:00 - 17:00)

"Design and Runtime Techniques for Leakage Control and Minimization of CMOS VLSI Circuits in Active and Sleep Modes,"
F. Fallah (FLA, USA) and Masaud Pedram (USC, USA)

ABSTRACT: In many new designs, the leakage component of power consumption is comparable to the dynamic component. Many reports indicate that 50% or even higher percentage of the total power consumption is due to the leakage of transistors and this percentage will increase with technology scaling unless effective techniques are used to bring leakage under control. This tutorial will focus on circuit techniques and design methods to accomplish this goal.
We will start the tutorial by describing the main sources of leakge in CMOS VLSI circuits and how these sources will scale with technology scaling. Next we will review a number of leakage current scenarios (ACTIVE and SLEEP mode), types of leakage control solutions (DESIGN vs. RUNTIME based solutions) and expected performance impacts. We will then present a few examples of DESIGN-based techniques for subthreshold leakage control. More precisely, we will explain how technology mapping can be modified to reduce the leakage through concurrent assignment of threshold voltages and transistor sizes as well as library cell selection. We will then describe a precomputation-based guarding technique, which reduces both the leakage and dynamic power and show the tool flow that may be used for applying it to an industrial VLIW processor. We will show how the low leakage of combinational gates, Flip Flops and bus drivers found in ASIC cell libraries can be reduced through circuit design and layout optimization techniques. The tutorial will be continued by presenting RUNTIME mechanisms for subthreshold leakage control. More specifically, we will talk about forward and backward biasing techniques and the transistor stacking technique. We will next present an algorithm for finding the minimum leakage vector of a circuit and show how the results can be improved by adding more controllability to a given circuit. One advantage of this method is that it can be applied to a sequential circuit without any delay overhead. We will also describe proven techniques for power gating and how to avoid potential power plane integrity problems. Finally, we will show how the gate-tunneling leakage can be reduced by using high threshold, thick-oxide sleep transistors. Another method for reducing the gate-tunneling leakage is using dual oxide technology. This method is analogous to the dual threshold technique for reducing the sub-threshold leakage. We will discuss how this method can be combined with the dual threshold technique to reduce both sub-threshold and gate-tunneling leakage.
Tutorial 3 (Full-day, 9:00 - 17:00)

"System-level Design Methodology for SoC Design,"
M. Fujita (Univ. of Tokyo, Japan), D. Gajski (UCI, USA), T. Imai (UCI, USA), and T. Hasegawa (Fujitsu, Japan)

ABSTRACT: This tutorial will cover basic concepts in system-level design, the design tasks, system-level (transaction-based) modeling, modeling languages, system-level synthesis and verification, and design methodology from specification to cycle-accurate design for systems on board, chip or embedded. Several speakers will define general design methodology, major issues in specification, synthesis and verification, and use of system-level methodology in different applications. The tutorial not only gives basic concepts present and future system-level design methodologies, but also presents and discusses a couple of real industrial design methodologies. Speakers will be from academia and industry covering both theoretical and practical issues on the design methodology.

Target audience: System-level or SoC designers, system and application SW engineers, IP and HW engineers, system managers, CAD developers and CAD researchers.

Table of content:
1. System-level methodology and design flow
2. Transaction-level modeling and synthesis
3. System-level languages and verification
4. System -level tools
5. Methodology examples
6. Product applications
Tutorial 4.1 (Half-day, 9:00 - 12:00)

"Low Power Design Techniques and Tools,"
S. Chattoapdhyay (Intel, USA) and R. Patel (Intel, USA)

ABSTRACT: We propose to deal with some aspects of design for low power (active and well as leakage power), device design basics with focus on the different types of leakage power and implications for a lower leakage device, VLSI CAD tools used in the industry to reduce power at the architectural, gate level (ASIC and Random cell based logic),transistor circuit level, physical design level, physical design (mask) level. Since leakage power is getting to be close to 40 % of the overall power in 90nm and 65nn designs we will emphasize on leakage power reduction.

The followings are list of contents:
I. Introduction to Low Power Design Techniques
II. Architectural Level Low Power Design
III. Device Design and I,plications on Low Power Design
IV. Low Power Memory/SRAM Design
V. Leakage Reduction Techniques
VI. Active Power Reduction Techniques
VII. Low Power Tools and Methodologies for ASIC/Custom designs
VIII Concluding Remarks

Intended Audience: VLSI design engineers, CAD tool developers, Design Automation Engineers, PhD research students, Graduate students focussing on Low power VLSI design, EDA tool Application Enginners
Tutorial 4.2 (Half-day, 13:30 - 16:30)

"Energy, Fault-tolerance, and Scalability Issues in Designing Network-on-Chip,"
R. Marculescu (CMU, USA)

ABSTRACT: The goal of this tutorial is to present the theoretical foundations and the design implications of using the Network-On-Chip (NOC) approach in designing the communication infrastructure of future Systems-On-Chip (SOCs). Step-by-step, the audience will be introduced to the key elements of this new communication paradigm, ranging from the properties of the underlying graphs, to possible implementations of complex applications via the NOC approach. Such a communication-centric design methodology addresses not only some of the short-term challenges related to IP-reuse and computation-communication separation of concerns, but also provides a robust solution for the long-term challenges imposed by the on-chip integration of mixed-technologies and mixed-design styles in next generation systems. Besides the mathematical models and basic design issues that are specific to SOCs, this tutorial will address in detail the interplay between the communication infrastructure and the communication paradigm on one side, and between the dissipated energy and the achievable performance, in the presence of complex failure mechanisms, on the other side. Indeed, as CMOS technology approaches the nanometer domain, the circuit behavior becomes more susceptible to process parameter variation, noise disturbances, high energy particles, etc. thereby necessitating some degree of built-in fault-tolerance during the system-level communication. This is important since a paradigm shift in the way we think about doing communication is really needed in order to build scalable and affordable systems on a single chip. Finally, the tutorial will illustrate the NOC-based communication in a practical setting with emphasis on the design issues that need to be considered for providing performance, scalability, fault-tolerance, and cost effectiveness.

Intended Audience: This tutorial is intended for researchers, engineers, students and educators trying to understand and utilize the NOC approach to solve their practical problems.

Tutorial Summary: By participating in this tutorial, the attendees will learn what the NOCs are all about and what they have to offer to the designers of future SOCs. Finally, the audience will get exposure to state-of-the-art NOC architectures and their practical implementation.

Contact to Tutorial Co-chairs (Hai-Gang Yang and Shinji Kimura)
Last modified: 2002.10.23