Photos of LSI Chips and a Test Board made at Feb. 2004

We are cooperating with VLSI Design Education Center (VDEC) at University of Tokyo, and we use the chip fabrication service via VDEC.

Students are welcome who are interested in the chip design.

FPGA chip with 3 x 3 LUT clusters, each of which includes 8 x 3-1 LUTs with novel function compaction mechanisms.

VDEC Rohm 0.35 micron, 4.9 mm x 4.9 mm
Chip for testing the functionality of several arithmetic operations, including multiplier, barrel-exchanger, etc.

VDEC Rohm 0.35 micron, 4.9 mm x 4.9 mm
A test bord of VDEC chip. All pins of a VDEC chip is connected to FPGA pins and we can apply test patterns and aquire output pattens via FPGA.

This is planned by Takeshi Ikenaga (and me) in our graduate school and made by MMS. We should thank to Kazutoshi Kobayashi of Kyoto University for his comments on the functions of the board.

Basically we have developped a VDEC chip test board at NAIST and this one is the revised board. The NAIST board was designed by Masaki Nakanishi with the support of Takashi Horiyama and me at 2000 - 2001.

Last modified: 2004.03