List of Publications

2006 (H18: 2006.04 - 2007.03)

• Transactions, Journals, and International Conference
  1. Nobuhiro DOI, Takashi HORIYAMA, Masaki NAKANISHI, and Shinji KIMURA,
     "Bit-Length Optimization Method for High-Level Synthesis based on Non-Linear Programming Technique,"
     IEICE Trans. Fundamentals, Vol. E89-A, No. 12, pp.3427-3434, Dec. 2006.
  2. Xingwen XU, Shinji KIMURA, Kazunari HORIKAWA, and Takehiko TSUCHIYA,
     "Coverage Estimation Using Transition Perturbation for Symbolic Model Checking in Hardware Verification,"
     IEICE Trans. Fundamentals, Vol. E89-A, No. 12, pp.3451-3457, Dec. 2006.
  3. Chengjie Zang, Shigeki Imai and Shinji Kimura,
     "Performance and Energy Efficient Data Cache Architecture for Embedded Simultaneous Multithreading Microprocessor",
     International SoC Design Conference (ISOCC2006), pp.351-354, Oct. 2006.
  4. Taeseok Jeong, Chengjie Zang and Shinji Kimura,
     "An Efficient Instruction Issue Mechanism for Simultaneous Multithreading Microprocessor",
     International SoC Design Conference (ISOCC2006), Oct. 2006.
  5. Chengjie Zang, Shigeki Imai, and Shinji Kimura,
     "Performance and Energy Efficient Data Cache Architecture for Embedded Simultaneous Multithreading Microprocessor,"
     Proceedings of 13th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2006), pp.268-273, April 2006.
• Research Meetings of IEICE or IEICE
  1. 木村 晋二, "動的再構成可能配線について", 信学技報 VLD2006-2, pp.7-12, 2006年5月.
  2. 井上 敬太, シン唯頡, 木村 晋二, "回路変更を用いたプロトタイプ設計検証の 高速化手法", 情報処理学会研究報告, No. SLDM129/4, pp.113-118, 2007年3月.

Pulbications at 2005 (H17)