High Level Design and Verification
With the recent advances on integrated circuits, it
has been feasible to integrate a whole information
system on a single LSI chip. The design level becomes high
corresponding to the size of the system. In our laboratory,
we are working on the high level design methods using programming
language such as C language or Java, and the design verification
methods. The design verification is specific to hardware
design since the fabrication of a new LSI chip takes a
lot of time and expense. The penaly in the fabricated chips
is larger than the software products. The following list
shows the current themes.
- Bit Width (Bit Length) Optimization to Reduce the Area and Speed
in High-Level Synthesis
- C Language based Processor Design
- High Level Equivallence Checking for Hand Optimization
- High Level Verification Based on the Logic Function Manipulation
Methods such as BDD and SAT
and Its Application
Reconfigurable hardware such as Field Programmable Gate Arrays
(FPGA) has an ability to change its functionality after the
fabrication. So reconfigurable modules behaves as a kind of
software, whose bug can be fixed by rewriting. Reconfigurable
hardware is widely used in the prototyping of application
specific hardware for functional verification. The architecutre
of FPGA is basicully suffer from the large area and slow speed
for implementing some module compared to ASIC. We are working
on the novel architectures of FPAGs and their applications.
- A new Look Up Table based FPGA with Folding Mechanism
- Reconfigurable Modules in a Multi-Thread Processor
- Mapping Algorithms for FPGA
Design and Implementation
of System LSI Chips
For the feasibility study of our design, we are developing
several LSI chips per year. We have been collaborating with
VLSI Design Education Center (VDEC) at University of Tokyo.
When designing LSI chips, we are searching new design methods
and verification methods.
- Cryptosystem LSI chips
- Real Time Processing LSI for Audio and Visual Data
- Reconfigurable Java Processor
- Multi-Thread Processor
Compression Methods of
Test Data and
At the fabrication of LSI chips, we should generate very thin
layers and lines, so it is hard to guarantee the correctness.
So the test of all chips is necessary for the correctness in the
fabrication, where test patterns are applied to all chips and
their outputs are analyzed whether the response if correct or not.
The test is rather time-consuming tasks and the number of
test patterns is the main factor of the test time. We are working
on the compression of test vectors and test methods for System
on a Chip Design. We also working on the interfaces of testers.
- Compression of Test Vectors
- Analysis of Tester Languages